A CMOS device comprises an N channel FET device and an associated and interconnected P channel FET device. It is desirable to space the N channel FET and P channel FET as closely as possible so as to increase the number of FETs which can be located in a given surface area. However, a widely recognized problem, commonly referred to as latchup, has the potential for occurring during the operation of CMOS devices that have closely spaced, i.e., a high packing density of, FETs. When CMOS devices are made in bulk semiconductor material, the N channel and P channel FETs are typically formed in a monocrystalline epitaxial layer which is disposed on a monocrystalline substrate. Such devices are typically referred to as bulk CMOS devices (as opposed to devices that are made on insulating substrates such as sapphire and which are commonly referred to as CMOS/SOS devices).
A variety of techniques have conventionally been used in an effort to reduce the susceptibility of bulk CMOS devices to latchup. These techniques include trench isolation as elaborated upon in TRENCH ISOLATION PROSPECTS FOR APPLICATION IN CMOS VLSI, R. D. Rung, IEDM Technical Digest, December, 1984, pp 574-577 and in U.S. Pat. No. 4,507,158, TRENCH ISOLATED TRANSISTORS IN SEMICONDUCTOR FILMS, T. I. Kamins et al., Mar. 26, 1985, and the use of heavily doped substrates or buried layers as disclosed in A NEW METHOD FOR PREVENTING CMOS LATCH-UP, K. W. Terrill et al., IEDM Technical Digest, December, 1984, pp 406-409. Trench isolation places a physical barrier between the N channel and P channel FETs. The use of heavily doped substrates provides a high conductivity, short minority carrier lifetime region beneath the FETs, thereby impeding the flow of minority carriers between the N channel and P channel devices.
The use of trench isolation in an epitaxial layer which is disposed on a heavily doped substrate still presents certain problems, however. When a heavily doped substrate is used, the epitaxial layer thereon is typically on the order of approximately 15 microns thick. This thickness is required in order to prevent the outdiffusion of impurities from the substrate during processing of the FETs. However, with conventional semiconductor processing techniques trenches of only 1 to 2 microns in depth are the deepest which are practicable. Deeper trenches create too large a number of crystalline defects to be acceptable. Thus, a 1 to 2 micron deep trench in a 15 micron thick epitaxial layer leaves a distance of 13 to 14 microns above the substrate/epitaxial layer interface in which latchup can occur.
As an alternative means for avoiding the aforementioned latchup problem in bulk CMOS devices, certain types of hybrid structures have been developed. These hybrid structures essentially provide a silicon-on-insulator (SOI) structure, such as silicon-on-sapphire (SOS), on the surface of a bulk semiconductor substrate. Examples of such hybrid structures may be found in COMPARISON OF DIFFERENT SOI TECHNOLOGIES: ASSETS AND LIABILITIES, L. L. Jastrzebski, RCA Review, June 1983, Vol. 44, pp 250-269, in U.S. patent application Ser. No. 608,544,J. F. Carboy, Jr. et al., METHOD OF GROWING MONOCRYSTALLINE SILICON THROUGH A MASK LAYER, filed May 10, 1984, now U.S. Pat. No. 4,578,142, and in the previously cited U.S. Pat. No. 4,507,158. Basically, these hybrid structures incorporate islands of an insulator such as silicon dioxide on the surface of a silicon substrate and monocrystalline silicon deposits on these insulator islands. The monocrystalline silicon deposits are isolated from the silicon substrate by the insulator islands, and the FETs which are to be isolated from each other are fabricated in the isolated silicon islands.
However, problems have also been observed with these "totally isolated" silicon island structures. One problem, termed charge pumping, is described in SOI BY CVD: AN OVERVIEW OF MATERIAL ASPECTS AND IMPLICATIONS OF DEVICE PROPERTIES, L. Jastrzebski, et al. Mat Res. Soc. Symp. Proc., Vol. 23, 1984, pp 417-430, and refers to the buildup of charge which can occur within a silicon island when the gate of the transistor therein is switched at high, e.g. nanosecond, speeds. These totally isolated structures may also prove to be uneconomical to manufacture because of the more lengthy processing associated with forming a complete epitaxial layer over the insulator layer (prior to defining the silicon islands) and because of the dimensional constraints on the insulator layer.